This application is based on the earlier Japanese patent applications No. 11-304683 (filed on Oct. 26, 1999) and No. 2000-308262 (filed on Oct. 6, 2000), the priority thereof under the Paris Convention is claimed. The entire disclosures thereof are incorporated herein by reference thereto.
This invention relates generally to an active matrix liquid crystal display device, particularly, to an active matrix substrate and a manufacturing method therefor. More particularly, it relates to a channel protection active matrix substrate in which a gate electrode, a drain electrode and a pixel electrode are isolated from layer to layer and the pixel electrode is formed as the topmost layer, and a manufacturing method therefor.
An active matrix liquid crystal display device, employing an active element, such as a thin-film transistor, is thin in thickness and lightweight, and is utilized as a flat panel display of a high picture quality. For a liquid crystal display device, a vertical electrical field system (typically formed as a twisted nematic or TN system) in which a liquid crystal is sandwiched between two substrates carrying transparent electrodes and is driven by a voltage applied across these electrodes, and a lateral (in-plane) electrical field system in which a liquid crystal layer is sandwiched between and driven by comb-shaped pixel electrodes in which the voltage is applied generally along the plane of the electrodes. In both systems, researches are conducted towards simplifying the production process of an active matrix substrate for lowering the production cost. On the other hand, the opening ratio needs to be raised for achieving a high-grade picture. To this end, such a method is used in which a transparent electrode (indium tin oxide or ITO) layer and a drain layer are isolated on the layer basis and the transparent electrode layer is formed as a topmost layer.
In the TN system, a liquid crystal is sandwiched between two substrates each of which is provided with a transparent electrode. In the lateral electrical field system, also called the in-plane switching (IPS) system, a liquid crystal layer is sandwiched between two substrates, each of which is provided with the transparent electrode, with the liquid crystal being driven by a voltage applied generally in-plane across a comb-shaped pixel electrode and a common electrode formed on one of the substrates.
As a manufacturing method in which the transparent electrode layer is formed as the topmost layer to simplify and diminish the number of steps of the production process, a technique shown in JP Patent Kokai JP-A-10-68971 is explained with reference to FIG. 62, which is a cross-sectional view for schematically showing the processes of the manufacturing method for an active matrix substrate for use in a TN system liquid crystal display device.
In general, the active matrix substrate of the TN system is comprised of a gate wiring lines and a drain wiring lines extending in a direction perpendicular to each other, a pixel electrode defined in an area surrounded by these wiring lines, and a thin-film transistor (TFT) formed in the vicinity of the intersection of the two wiring lines. On the surface of the TFT is formed a channel protection film for assuring the performance. On the TFT and the pixel electrode on the active matrix substrate, there is formed an orientation film for orienting the liquid crystal in the pre-set direction. A liquid crystal is sealed between the active matrix substrate and a counter substrate carrying a color filter, a common electrode and an orientation film to complete the liquid crystal device.
In this active matrix substrate, a gate electrode metal film of, for example, Cr, is deposited on the transparent insulating substrate 101, a resist pattern is formed, using a first photomask, and the exposed portion of Cr is etched to form a gate wiring and a gate electrode layer 102 branched from the gate wiring, as shown in FIG. 62(a).
Then, a gate insulating film 103 of SiNx, an a-Si layer 104, a n+ type a-Si layer 109, as an ohmic contact layer, and a drain electrode layer 106 of e.g., Cr, are deposited in succession, after which an unneeded drain electrode layer 106 is selectively etched, in order to form an opening in the channel area of the a-Si layer 104 and a preset wiring pattern, as shown in FIG. 62(b). Then, using the drain electrode layer 106 as an etching mask, the n+type a-Si layer 109 is etched to form an ohmic contact layer.
Then, a second passivation film 107, such as SiNx, is deposited on the entire substrate surface, and the preset areas of the second passivation film 107, a-Si layer 104 and the gate insulating film 103 are collectively etched using a third photomask, to separate the thin-film transistor area, as shown in FIG. 62(c).
Then, a contact hole for exposing a source/drain electrode areas is formed, using a fourth photomask, ITO film 108 is deposited on the entire surface of the substrate 101, and the ITO film 108 in the preset area is removed, using a fifth photomask, to form a pixel electrode connected to the source electrode, to complete the production of the active matrix substrate, as shown in FIG. 62(d).
It is noted that a contact hole exposing the source/drain electrode areas is formed in the second passivation film 107.
In this conventional active matrix substrate, the ITO film 108 is not provided on the same layer as the source/drain electrode layer 106, and is insulated and separated by the second passivation film 107. So, for insulation and isolation of the ITO film 108 from the drain electrode layer 106, these are not in need of being separated from each other laterally relative to a normal line drawn to the active matrix substrate, and hence these can be made to approach extremely closely to or even overlap with each other. Thus, the black matrix for shielding the uncontrolled back light straying from a gap produced when the ITO film 108 and the source/drain electrode layer 106 are separated from each other can be diminished to elevate the opening ratio. This accounts for insulation and separation of the ITO film 108 and the drain electrode layer 106 from each other by the second passivation film 107.
It is noted that the ITO film 108 is insulated and separated from each other by the passivation film 107. In this conventional method for preparing the active matrix substrate, the active matrix substrate can be produced by five masks as the transparent electrode layer is formed as the uppermost layer.
Various problems have been encountered in the course of investigations toward the present invention.
In the method, shown in the above-mentioned Publication, the gate electrode, drain electrode and the pixel electrode of ITO film are isolated on the layer basis by five masks to produce an active matrix substrate carrying a topmost ITO film. There is, however, presented a problem that, since the second passivation film 107, a-Si layer 104 and the gate insulating film 103 are etched in a lump at the process step of FIG. 62(c), the lateral surface of the a-Si layer 104 is exposed without being covered by the second passivation film 107.
If the lateral surface of the a-Si layer 104 is exposed, it is caused to contact the ITO film 108 formed subsequently. Moreover, if the active matrix substrate is configured as a liquid crystal device, the liquid crystal material directly contacts the a-Si layer 104.
If the ITO film 108 contacts the lateral surface of the a-Si layer 104, not covered by the pass i vat ion film, the metal as a constituting component of the ITO film 108 is diffused as impurity into the inside of the a-Si layer 104, thereby appreciably deteriorating the performance of the thin-film transistor. For evading this problem, the passivation film can again be deposited after the step of FIG. 62(c) and before the step of FIG. 62(d) to protect the lateral side of the a-Si layer 104 with the passivation film. There is, however, raised a problem that deposition of the passivation film a second time increases the number of process steps.
On the other hand, if the ITO film 108 contacts the sidewall section of the a-Si layer 104 not covered by the passivation film, impurities in the liquid crystal material is similarly diffused into the a-Si layer 104 to produce a similar phenomenon.
In general there is much to be desired in the conventional art and it is desired to provide a novel device and method.
In view of the above-mentioned problem, in an aspect of the present invention, it is an object thereof to provide an active matrix substrate in which an active matrix substrate of the channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another on the layer basis by insulating films can be formed by four masks, and a manufacturing method for the active matrix substrate.
In another aspect of the present invention, it is another object thereof to provide a channel protection type active matrix substrate in which a gate electrode, a drain electrode and a pixel electrode are separated from one another on the layer basis by insulating films to assure superior long-term reliability, and a manufacturing method therefor.
Other aspects and objects will become apparent by the entire disclosure.
According to the present invention, there is provided in its first aspect, an active matrix substrate wherein a gate electrode layer, a gate insulating layer and an amorphous silicon semiconductor layer are deposited in a substantially stacked (or laminate) fashion on a transparent insulating substrate, viewed from a direction normal to the transparent insulating substrate, to form a layered (stacked laminate) structure, including a gate electrode, a gate wiring (generally in the form of lines) and a thin-film transistor area. The active matrix substrate includes: a drain wiring formed on a first passivation film disposed on the substrate so as to cover the layered (stacked laminate) structure. There is a second passivation film formed as an overlying layer above the drain wiring and the first passivation film. There is also formed source/drain openings passing through the first passivation film and the second passivation film to reach a amorphous silicon semiconductor layer. There is also an opening passing through the second passivation film to reach the drain wiring connection. Further, a wiring (connection) layer extending through the aforementioned opening and/or openings is formed, for establishing connection, by a pixel electrode film disposed on the second passivation film.
The present invention also provides, in its second aspect, a vertical electrical field type active matrix substrate wherein a gate electrode layer, a gate insulating layer and an amorphous silicon semiconductor layer are deposited in a substantially stacked fashion on a transparent insulating substrate, viewed from the direction normal to the transparent insulating substrate, to form a layered structure, including a gate electrode, a gate wiring (generally of lines) and a thin-film transistor area. The substrate includes a drain wiring (generally of lines) formed on a first passivation film (disposed on the substrate and) covering the layered structure. There is a second passivation film formed as an overlying layer above the drain wiring and the first passivation film. There are also formed source/drain openings passing through the first passivation film and the second passivation film to reach the amorphous silicon semiconductor layer. There is also an opening passing through the second passivation film to reach the drain wiring. Further, a wiring layer (connection) connecting (extending) through the drain opening to the drain wiring and a pixel electrode connected (extending) to the source opening are formed by a pixel electrode film disposed on the second passivation film. The pixel electrode is provided with a storage capacitance unit, comprised of the first and second passivation films sandwiched between the pixel electrode and an electrode layer formed as a co-layer as the gate electrode.
Generally, the substrates of the present invention are used installed and assembled in an active matrix liquid crystal display device.
The present invention also provides, in its third aspect, a novel method for producing an active matrix substrate. The method comprises the steps of:
(a) layering a gate electrode layer, a gate insulating film and an a-Si layer in this order on a transparent insulating substrate and forming a gate electrode, a gate wiring and a thin-film transistor area, using a first mask,
(b) depositing a first passivation film and a drain electrode layer on the gate electrode, and removing the drain electrode layer lying in a pre-set area, using a second mask, to form a drain wiring,
(c) depositing a second passivation film above (as an overlying layer of) the drain wiring, forming openings at preset positions in the amorphous silicon semiconductor layer passing through the first and second passivation films for connection to the source/drain electrodes (i.e. source electrode/drain electrode), an opening, above the drain wiring, passing through the second passivation film, and
(d) depositing a transparent electrode layer as an overlying layer on the second passivation film and on (and within) the opening(s), to form a drain wiring connection connecting to an amorphous Silicon layer exposed in the opening for the drain electrode, using a fourth mask, and connecting the amorphous silicon layer exposed in the opening for the source electrode to a pixel electrode comprised of the transparent electrode layer.
Other aspects and features of the present invention are disclosed in the appended claims, the entire disclosure thereof being incorporated herein by explicit reference thereto.